Is the AI chip dead? What Arm’s new CPUs mean for your next Android phone

The conversation around mobile AI has been dominated by talk of NPUs, TPUs, and dedicated neural accelerators. But what if your phone’s general-purpose CPU could shoulder that burden instead? Arm is betting big on exactly that with its new C2-Ultra, the powerhouse architecture set to define the next generation of 2027 flagships — from the latest MediaTek and Samsung silicon to, perhaps, Google’s future Tensor chipsets.

Arm’s pivot here is interesting, if that’s the right word. Shifting focus away from just pushing higher clock speeds and pipeline width towards accelerating more specialist use cases has potentially significant upsides if those workloads stick around. However, there’s no guarantee the market won’t keep demanding ever-higher peak general performance, particularly as mobile and PC use cases continue to collide.

So let’s dig into this year’s C2-Ultra, -Premium, -Pro, and -Nano CPU cores to see what this revised strategy entails.

The headline CPU announcement from Arm this year is the C2-Ultra, the powerhouse successor to last year’s C1-Ultra. While Arm does not confirm partner products ahead of time, the usual cadence of silicon releases means this new core is likely headed to next-gen Samsung Exynos and MediaTek Dimensity chipsets for phones around the turn of 2027. We might even see it in Google’s next-gen Tensor G7, if we’re lucky.

For headline figures, Arm says the core boasts up to 15% improved peak performance over its predecessor. However, a clock speed boost to a rather speedy 4.45GHz accounts for 8% of the performance improvements, so only the remaining 7% comes from core architecture improvements. Perhaps more importantly, the core can deliver the same performance as last year’s model while reducing power consumption by 38%, thanks in no small part to the move to 2nm. C2-Ultra can now have up to 3 MB of L2 cache, a useful performance upgrade for processors willing to trade silicon area for memory.

What’s interesting, and perhaps a little unusual for Arm, the C2-Ultra pipeline is the same width as the C1-Ultra. The performance improvements aren’t coming from doing more work with each clock cycle. Instead, Arm has boosted the C2-Ultra’s execution window by 30%, meaning there are around 2600 instructions in flight at any one time, compared to 2000 in C1-Ultra. Likewise, Arm has beefed up its out-of-order execution mechanisms with smarter speculation and faster recovery, enabling earlier detection and execution of code dependencies by analyzing the workload and data types.

The general idea is that the C2-Ultra spends less time waiting for data and, where possible, selects important code to run in the optimal order. Removing these bottlenecks slightly speeds up execution and reduces power consumption by reducing the time spent moving data between caches.

Unfortunately, the C2-Premium, C2-Pro, and C2-Nano haven’t received such sweeping updates. They are essentially the same core architecture as last year’s C1 variants, but tweaked for area, efficiency, and power on next-generation 2nm manufacturing lines.

No 2026 announcement is complete without AI, and Arm’s C2 CPU announcement is no different. In addition to the 15% general performance gain, Arm boasts its next-gen CPU configuration can provide up to a 1.7x performance improvement in AI models by further accelerating low-precision math and utilizing Lookup Table Instructions (LUTi) to reduce memory bandwidth demands.

This is accomplished by placing two Scalable Matrix Extensions (SME2) units into the shared CPU cluster, rather than the single unit supported last year. However, the new Xiaomi XRING O3 supports dual SME2 units with last year’s C1 architecture, so this doesn’t appear to be a hard rule.

In any case, the important thing about SME2 is that its code executes as part of the regular CPU instruction pipeline. This means no additional software developer work is required to support enhanced AI acceleration on supported CPUs, aside from ensuring the instructions are compiled into the code. Moving up to two SME2 units, however, doesn’t double the throughput outright. Instead, the units execute in parallel, providing a performance uplift in scenarios where AI workloads can be split up. It’s not a free lunch, but Arm’s reference platform also suggests higher SME2 clocks are achievable this year (up to 3GHz, up from 2GHz), so it’s clear that AI workloads stand to benefit the most with this coming generation.

For real-world use cases, Arm benchmarks a 40% reduction in speech-to-text latency, ensuring near-instantaneous voice recognition. Memory retrieval search latency is now 41% faster, allowing the system to recall user preferences and past interactions with minimal delay. Finally, prompt generation speed improves by 25% in time-to-first-token, making on-device machine learning models feel more responsive.

As is always the case with Arm’s announcements, it just lays out the core parts; it’s up to its silicon partners to bundle these into the complete configurations. Presentation slides reference designs range from 2x C2-Pro/4x C2-Nano configurations for budget devices to 2x C2-Ultra and 6x C2-Pro cores for flagship-tier products, with peak clock speeds of 4.45GHz on the largest cores and 3.6GHz for Pro cores. Obviously, the exact configurations, clocks, cache, SME2, and other configuration options vary by vendor.

If 2025/2026 products are anything to go by, we will certainly see one or two of the largest C2-Ultra cores used to deliver robust peak performance, paired with C2-Premium and C2-Pro cores for sustained and multitasking workloads, and an SME2 unit (or two) on ultra-premium chips to help accelerate AI.

Arm notes that we should expect a 10- to 12-core CPU configuration from at least one of its partners later this year, which is presumably the MediaTek Dimensity 9600. Keep your eyes peeled for more partner announcements as we approach 2027.