IBM announced that it has built the world’s first sub-1nm chip technology, a transistor architecture at what it calls the 0.7nm, or 7-angstrom, node.
It is the kind of milestone the semiconductor industry has been straining toward for years, and the kind of claim that needs reading carefully, because a node name is no longer a measurement of anything physical.
The technology rests on a design IBM calls “nanostack,” which the company describes as the industry’s first three-dimensional, nanosheet-based transistor architecture.
Rather than laying transistors out across a flat plane and shrinking the gaps between them, nanostack stacks and staggers them vertically, using 3D sequential integration to fit more onto the same footprint.
The approach also lets engineers use different material combinations in each stacked layer, tuning the performance and power of each transistor more or less independently.
The headline figure is density. IBM says the chip packs nearly 100 billion transistors onto a piece of silicon the size of a fingernail, close to twice the density of the 2nm chip it unveiled in 2021.
On the company’s own published results, the new node offers up to 50% more performance, or up to 70% better energy efficiency, than that 2nm generation.
Both of those are IBM’s projections from research results, not figures from a shipping product, and the two numbers describe different operating points rather than a single chip doing both at once.
There is supporting work behind the announcement. In research presented at VLSI 2026, IBM said nanostack delivers 40% scaling in SRAM, the fast on-chip memory that has stubbornly resisted shrinking in recent generations and that matters a great deal for the high-bandwidth demands of AI workloads.
The company also says it validated the architecture through dielectric bonding in CMOS integration and demonstrated a working CMOS inverter, which is to say it has shown the structure can be physically built and can switch, not merely simulated.
“With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built,” said Jay Gambetta, director of IBM Research.
The framing matters, because the industry left literal dimensional scaling behind some time ago. A “0.7nm” node does not mean any feature is 0.7 nanometres across; it is a generation label.
What IBM is claiming is that nanostack lets logic extend below the 1nm node for the first time, into what the company calls angstrom-scale territory, where dimensions approach the size of individual atoms.
The work was done at the Albany research complex in upstate New York, which is soon to house a High-NA EUV lithography tool from ASML, the next-generation machine seen as essential to printing circuits this small.
IBM credited partners including Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions, and noted its recent move to form Anderon, a standalone quantum foundry, as part of the same bid to keep advanced chipmaking onshore.
ASML’s High-NA tools have divided the industry on cost, with TSMC initially sceptical of the price.
The caveat is the one that attends every IBM chip announcement. The company sold its manufacturing business to GlobalFoundries in 2014 and now develops technology to be licensed and built by others.
So this is a research milestone rather than a product, and IBM puts the path to production at as early as five years out. That is a long runway, and a lot can change across it.
For now, IBM has a structure that works in the lab, a roadmap it says buys the industry another decade of scaling, and a node name that is really a statement of intent.
